This invention relates to bus arbitration, lock logic and more particularly to bus arbitration and lock logic for accessing of memory shared between multiple processors.
With the advent of desk top and personal computers, computer technology has spread to millions of users. The technology in these computers is typically limited in large part by the architecture of the host-processor used in the computer. Thus, personal computers utilized embedded microprocessors such as the ZilogZ80, Z80, Intel 8080, 8088, 8086, 80286, 80386, 80486, Motorola, 6800, 68000, 68010, 68020, 68030, 68040, and others. These were initially very limited both in processing speed, band-width, and memory space capabilities. These systems typically provided expansion or extension bus systems, to allow for the addition of additional peripheral circuit cards to the system, such as adding more memory, disk controllers, graphic interfaces, etc.
As the demand increased for faster and more powerful processing, add-on processor boards were created, where control was temporarily passed from the original embedded host processor to the add-on processor, but where only one processor was actually operating as the Monitoring and Control processor at a time. Thus, control is transferred between one or the other of these co-processors.
Current state of the art desk top and personal computers now offer high-speed 32 bit microprocessors, and custom processor chip sets. These processors provide many new architectures and techniques to maximize the performance of the systems. This includes the Intel 80386 microprocessor, the Motorola 68030, and various newly announced processors such as the Intel 80486, the Intergraph Clipper computer chip set originally pioneered by Fairchild Semiconductor, as well as many others. While these desk top computers and personal computers are primarily intended as a single processor system, capabilities can be provided for multiple processor operation through the use of a second processor. However, in previous systems, only one of these two processors can actually be accessing memory at any one time instance. A given bank of memory can only be accessed by one processor at a time. This greatly restricts parallel processing capabilities, because of the asynchronous nature of bus demands by a plurality of unrelated processors, and because of contention and crash conditions which are created in back-to-back locked memory cycles.
The many problems of a multiprocessor system are further complicated by the problem of how to correctly arbitrate between multiple processors which need to access a shared memory space. One solution attempted in the past has been to use the demand or lock cycle functions of the embedded host-processor, where such features are present, such as in the Intel 80386. The 80386 has both bus arbitration logic and lock (or demand) cycle status output information provided by its internal logic. Due to the pipelined nature of the 80386 host processor, the processor has knowledge ahead of time as to which future cycles will be locked and which will not be. Lock cycles protect data integrity by allowing two-step "test and set" operations, and other back-to-back locked memory cycles of the host processor, to be uninterrupted during the actual writes to memory.
In a single processor environment, this makes it possible for the on-chip bus arbitration logic to decide when to give the bus access away from the host-processor itself.
In the multiprocessor application, a posted write array allows the faster processor to post its writes to a slower bus, where the processor is then free to start another cycle even while the bus is independently completing the posted writes. Thus, the posted write queue provides for asynchronous access to the shared memory array via a common bus system, while allowing each processor in the multiprocessor system to continue to operate synchronously within its own subsystem.
However, the processor direct control of the bus arbitration solution cannot be utilized when a posted write array is present in the system to buffer writes between the processor and the bus. This is the case because the processor must run asynchronously relative to the bus arbitration system, and therefore the processor's internal bus arbitration circuitry will be out of phase with what is actually occurring on the external bus.
The 80386 host processor's internal bus arbitration unit selectively gives control of the bus away at what the processor considers as the end of the cycle. Without the presence of a posted write array, the end of the processor cycle is the same as the end of bus cycle, and the processor's internal bus arbitration logic is in phase with the bus, and it thus gives away the bus at the proper time.
However, when a posted write array is installed in the system, the end of the processor cycle is no longer guaranteed to match the actual end of the bus cycle on the bus. Thus, the processor's internal bus arbitration unit can no longer be singularly utilized, since it can give the bus away at the end of the processor's cycle which could be in the middle of the actual bus cycle. If the bus were to be given away in the middle of the actual bus cycle, there would be contention on the bus and the system would crash.
The Posted Write Array allows asynchronous operation by isolating and buffering the processor from the memory write, and takes over the intelligent management of writes to the memory. The processor is thus able to post its writes to memory at very high speed to the posted write array queue, which thereafter takes care of writing to the actual memory independent of and asynchronous to the processor which posted the write.
In accordance with the present invention, a bus arbitration system is provided which insures the correct accessing of memory that is shared between multiple processors, particularly in computer systems utilizing a posted write array to queue writes to the shared memory, and a processor that is capable of commanding that its right to access the bus cannot be given away through the use of a lock signal or equivalent status output. The main host processor can thus continue to run, out of local cache memory, for example, even while the second processor has access to the bus and is running.
The use of a posted write array, and its multiple-processor capabilities, requires the system to provide an external bus arbitration subsystem, separate from the bus arbitration unit inside the host-processor (such as an 80386). The design of the external bus arbitration unit itself can be embodied in any of a number of ways. However, to properly function, the external bus arbitration subsystem must properly interface with and utilize the lock status output from the processor. This lock output must be correctly processed and appropriately interfaced to the external bus arbitration unit so that correct arbitration of the bus system can occur.
The proper handling of the processor lock status output is required prior to processing by the external bus arbitration unit. In many host-processors, such as the 80386, their external LOCK status output is placed into a floating or inactive state during idle cycles, even during idle cycles which occur between locked cycles of the processor. Furthermore, with the use of a posted write array, the bus main memory can have back-to-back LOCKed cycles on the bus, while not actually having back-to-back locked cycles coming out of the processor.
The existence of these two conditions is important. The benefit of utilization of the LOCK status output is to prevent the bus from being given away between consecutive processor cycles which are locked. Proper handling of the LOCK status output is provided in accordance with the present invention, so that even as the LOCK status output from the processor goes invalid because of the presence of an idle cycle between two consecutive locked processor cycles, the bus will not be given away creating a contention problem. In a preferred embodiment, special handling of the lock status output is provided so that even if consecutive lock cycles do occur on the bus, the bus can be given away if the consecutive locked bus cycles did not originally occur as locked consecutive cycles from the processor.
In accordance with the present invention, the proper handling and preprocessing of the LOCK status output prior to coupling to the external bus arbitration unit is provided for, to avoid the above-mentioned problems.
To properly handle the processor lock signal going invalid during idle cycles, the system of the present invention provides a memory or logic to retain knowledge of the lock status of the current cycle and of the previous cycle whether or not an idle cycle occurred between them, and decision logic to determine whether to give the bus away, or not. If the cycle before the idle cycle was a non-locked cycle from the processor, then, if a bus request is pending, the bus can be given away. However, if the cycle immediately preceding the idle cycle was a locked cycle from the processor, then the bus cannot be given away until the idle cycle is over and the next cycle begins. The bus cannot be given away in this instance until the next cycle begins, because it is only then that a LOCKED status of the cycle which is about to begin will actually be known. If this next (new) cycle is locked, then there will have been two back-to-back locked cycles from the processor, and the bus cannot yet be given away. However, if this new cycle is non-locked from the processor, then the bus can be given away before this new cycle starts on the bus. The decision logic properly utilizes the stored data from the memory to provide for restricted and controlled access to a shared memory so as to prevent conflict or loss of data integrity.